1. Technical Field
The present invention relates to logic circuits, and more particularly relates to a domino circuit design for handling high stress conditions.
2. Related Art
Domino logic circuit design techniques have become widely used for applications requiring high performance. Such designs offer significant speed advantages over logic circuits employing more traditional designs, such as those that utilize pass gate or static logic designs. In particular, because domino logic circuits employ a "precharge" state, they can be switched much quicker than a comparable static logic circuit.
FIG. 1 illustrates a typical domino gate circuit 10, in this case a pseudo two-way AND logic gate. The circuit includes a PFET 16 that acts as a precharge device, a PFET 18 that acts as a keeper device, an inverter buffer 20, an output 24, a precharge input PC, an NFET 26 that is referred to as foot switch, a pair of NFETs 12 and 14 that comprise evaluate inputs A and B, and precharge node Node E. The circuit operates in two phases, the precharge phase and the evaluate phase. During the precharge phase, PC is low therefore causing precharge device 16 to charge Node E to Vdd. Accordingly, inverter buffer 20 causes the output 24 to go low and keeper device 18 to turn on causing Node E to be maintained or "kept" at Vdd. During the evaluate phase, PC goes high and the foot device 26 turns on which allows for the evaluation of inputs A and B. Thus, if A and B are both high, Node E is discharged to ground, and output 24 goes high. Alternatively, if A and/or B were low, Node E would remain at high due to the capacitance existing at node E. Keeper device 18 prevents Node E from drooping during the evaluation due to various leakage mechanisms. The keeper device 18 is generally a weak device, presenting very little hysteresis (or delay) during times when inputs A and B go high to pull down Node E. Keeper device 18 also guards against noise on Node E, but because of its size, it is insufficient to provide substantial noise immunity.
Once the evaluation is complete and PC is again active, it is desirable to quickly recharge Node E to Vdd. Therefore, precharge device 16 must be of sufficient size to meet this requirement. Accordingly, for high performance logic paths, precharge device 16 is necessarily much larger than keeper device 18. For example, if precharge device 16 were to have a width to length ratio of 1/1, keeper device would likely have a width to length ratio of 1/3.
As noted, keeper device 18 has two important functions, namely to maintain the charge at Node E by replacing charge loss to leakage, and to provide noise immunity. By minimizing the relative size of keeper device 18, Node E becomes easier to discharge during a logic function evaluation, therefore resulting in higher speed and performance. In other words, as the relative size of the keeper device 18 is increased, increased hysteresis is introduced onto Node E therefore resulting in decreased performance. As such, it is desirable to keep the keeper device 18 relatively small so that Node E can maintain its charge and operate as quickly as possible. However, the size of the keeper device must be large enough to replace leakage charge. If device 18 is sized large to contribute significant noise immunity, the performance suffers substantially. Thus, depending on the level of noise immunity required, a significant performance limitation may be introduced.
As with many of today's more advanced and critical integrated circuit devices, it is necessary to perform extensive reliability testing on chips containing domino circuits as part of the quality assurance procedure. Such tests seek to stress the integrated circuit device beyond its normal operating range to expose defects. During one such test, referred to as "burn-in," the chip is run at an elevated voltage and temperature. Accordingly, domino circuits, such as the one depicted in FIG. 1, must be designed with increased functionality margin. In particular, because Vdd will be set at an elevated level, noise effects on Node E or increased subthreshold leakage effects on Node E can result in a potential failure, particularly if keeper device 18 is small. As such, during burn-in, as opposed to normal operations it is desirable for keeper device 18 to be relatively large. Because high performance is not needed during burn-in (the device under stress is operated at a much reduced frequency) the operation of precharge device 16 becomes far less critical so size is not as important.
At elevated voltages, the risk of failure of a domino circuit is greater because incident noise is substantially worse. Referring still to FIG. 1, consider the case where input A is low and B is high during the evaluate phase. Node E should remain at or near Vdd which would result in an output 24 value of low. However, capacitive coupling on the input A is larger during burn-in and can potentially erode the Node E precharge. Thus, during burn-in there may be sufficient noise present to pull Node E low and erroneously flip the output. Thus, a need exists to provide a domino circuit that can protect against failures during burn-in while providing high performance during normal functionality.